The MPC team is participating to the SC20 online events, both as member of the Architecture and Network committee and authors/co-authors of two papers in SC workshops. Do not miss the paper “PARCOACH Extension for Static MPI Nonblocking and Persistent Communication Validation” in the CORRECTNESS workshop, Wednesday 11th November, 5:15PM EDT. Enjoy the paper “Application-Driven…
The MPC team will participate in the September 2020 Virtual MPI Forum Meeting, which replaces the September 2020 MPI-Forum face-to-face meeting due to the COVID-19!
The MPC team will be at the online edition of IWOMP 2020 and will present a paper titled “Preliminary Experience with OpenMP Management Implementation Memory” on Thursday 24th September 2020, 12 PM.
The MPC team will participate to the online edition of the EuroMPI 2020 conference.The team will present a paper titles “Implementation and performance evaluation of MPI persistent collectives in MPC : a case study” on Tuesday 22th September, 12PM EST.
The MPC team participated in the virtual MPI Forum Meeting, which took place instead of the June 2020 MPI-Forum face-to-face meeting due to the COVID-19!
MPC v3.4.0 is now available! Here are the new additions: Active Message Integration of custom Active Messages relying on gRPC approach MPI: Optimizations and corrections of nonblocking collectives Bugfix on virtual topologies (MPI_Cart_*) OpenMP: Improved OMPT support Bugfix on tasks with dependencies Network/communication layers Support of MPI Hardware-enabled operations through Portals4 driver Privatization / compilers…
The MPC team will be in Portland, OR, for the February 2020 MPI-Forum face-to-face meeting!
MPC is at Seattle, Washington, USA, for the SIAM PP 2020 conference. Please, come join us at MiniSymposium MS8, entitled Co-Design of Networking for Scientific HPC Applications , on Wednesday Afternoon 1PM in room 604, for the presentation “Network Bottleneck Handling in Multi-Threaded MPI Context“
Today, a training on MPC specific features for efficient MPI+X programming takes place at the Ter@tec Building, in Bruyères-le-Châtel, France.
CEA and MPC team, in collaboration with other French, EU and US institutions, proposed a new workshop focusing on compiler techniques for parallelism in HPC. This workshop called Compiler-assisted Correctness Checking and Performance Optimisation for HPC, or C3PO-4-HPC, has been accepted as a Full day workshop at ISC 2020.